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<A name="Par"></A>                         Lattice PAR Report File
Radiant Software (64-bit) 2024.2.0.3.0
Tue Mar 18 14:17:22 2025

Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -hsp m -exp parPathBased=ON \
	ICE40UP5K1_impl_1_map.udb ICE40UP5K1_impl_1.udb 


<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/       Number       Estimated       Timing       Estimated Worst    Timing          Run      Run
Cost [udb]   Unrouted     Worst Slack     Score        Slack(hold)        Score(hold)     Time     Status
----------   --------     -----------     ------       ---------------    -----------     ----     ------
5_1   *      0            30.353          0            1.743              0               01:28    Completed
* : Design saved.

Total (real) run time for 1-seed: 1 mins 29 secs 

par done!


<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Radiant Software (64-bit) 2024.2.0.3.0.
PARed on: Tue Mar 18 14:17:22 2025

Command Line: par -w -t 1 -cores 1 -hsp m -exp parPathBased=ON \
	ICE40UP5K1_impl_1_map.udb ICE40UP5K1_impl_1_par.dir/5_1.udb 

Loading ICE40UP5K1_impl_1_map.udb ...
Loading device for application GENERIC from file &apos;itpa08.nph&apos; in environment: D:/radiant/ispfpga.
Package Status:                     Preliminary    Version 1.5.
Performance Hardware Data Status:   Advanced       Version 1.0.



Design:  top_module
Family:  iCE40UP
Device:  iCE40UP5K
Package: SG48
Performance Grade:   High-Performance_1.2V
WARNING: Cannot have multiple create_clock constraints with the same clock name: &quot;clk&quot;. This constraint &quot;create_clock -name {clk} -period 83.33 [get_nets clk]&quot; will be ignored. Please check constraint usage carefully (e.g. duplications, conflicts, etc.)!


<A name="par_constraint"></A><B><U><big>Constraint Summary</big></U></B>
   Total number of constraints: 17
   Total number of constraints dropped: 0

WARNING &lt;70009502&gt; - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
Number of Signals: 5399
Number of Connections: 17728

<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>

   SLICE (est.)    2243/2640         85% used
     LUT           4289/5280         81% used
     REG            801/5280         15% used
   PIO               12/56           21% used
                     12/36           33% bonded
   IOLOGIC            0/56            0% used
   DSP                0/8             0% used
   I2C                0/2             0% used
   HFOSC              1/1           100% used
   LFOSC              0/1             0% used
   LEDDA_IP           0/1             0% used
   RGBA_DRV           0/1             0% used
   FILTER             0/2             0% used
   SRAM               0/4             0% used
   WARMBOOT           0/1             0% used
   SPI                0/2             0% used
   EBR                5/30           17% used
   PLL                0/1             0% used
   RGBOUTBUF          0/3             0% used
   I3C                0/2             0% used
   OPENDRAIN          0/3             0% used

Pin Constraint Summary:
   12 out of 12 pins locked (100% locked).

Finished Placer Phase 0 (HIER). CPU time: 18 secs , REAL time: 19 secs 


...................................
Finished Placer Phase 0 (AP).  CPU time: 31 secs , REAL time: 32 secs 

Starting Placer Phase 1. CPU time: 31 secs , REAL time: 32 secs 
..  ..
....................

Placer score = 1018825.

Device SLICE utilization summary after final SLICE packing:
   SLICE           2245/2640         85% used

WARNING &lt;70009502&gt; - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
Finished Placer Phase 1. CPU time: 54 secs , REAL time: 56 secs 

Starting Placer Phase 2.
.

Placer score =  1240298
Finished Placer Phase 2.  CPU time: 56 secs , REAL time: 57 secs 



<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>

Global Clocks :
  PRIMARY &quot;clk&quot; from comp &quot;OSCInst0.osc_inst&quot; on site &quot;HFOSC_R1C32&quot;, clk load = 435, ce load = 0, sr load = 0
  PRIMARY &quot;flicker_N_2264&quot; from F1 on comp &quot;u3_time_cal.u2_beeper_ctrl.SLICE_3974&quot; on site &quot;R14C3B&quot;, clk load = 0, ce load = 0, sr load = 430
  PRIMARY &quot;u8_ws2812.n31639&quot; from F1 on comp &quot;u8_ws2812.SLICE_2368&quot; on site &quot;R13C3C&quot;, clk load = 0, ce load = 75, sr load = 0
  PRIMARY &quot;u7_oled_chinese.n31631&quot; from F0 on comp &quot;u7_oled_chinese.SLICE_3299&quot; on site &quot;R14C31C&quot;, clk load = 0, ce load = 59, sr load = 0

  PRIMARY  : 4 out of 8 (50%)




I/O Usage Summary (final):
   12 out of 56 (21.4%) I/O sites used.
   12 out of 36 (33.3%) bonded I/O sites used.
   Number of I/O components: 12; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+---------------+------------+------------+------------+
| I/O Bank | Usage         | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+---------------+------------+------------+------------+
| 0        | 6 / 14 ( 42%) | 3.3V       |            |            |
| 1        | 1 / 14 (  7%) | 3.3V       |            |            |
| 2        | 5 / 8 ( 62%)  | 3.3V       |            |            |
+----------+---------------+------------+------------+------------+

Total Placer CPU time: 56 secs , REAL time: 57 secs 


Checksum -- place: 2b86cd30d1f6eae3915923f5ec93fd0460ed4b6
Writing design to file ICE40UP5K1_impl_1_par.dir/5_1.udb ...


Start NBR router at 14:18:20 03/18/25

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in timing report. You should always run the timing    
      tool to verify your design.                                
*****************************************************************

Starting routing resource preassignment
Preassignment Summary:
--------------------------------------------------------------------------------
3 global clock signals routed
2061 connections routed (of 16777 total) (12.28%)
---------------------------------------------------------
Clock routing summary:
Primary clocks (4 used out of 8 available):
#0  Signal &quot;flicker_N_2264&quot;
       Control loads: 430   out of   430 routed (100.00%)
#1  Signal &quot;u7_oled_chinese.n31631&quot;
       Control loads: 59    out of    59 routed (100.00%)
#4  Signal &quot;clk&quot;
       Clock   loads: 435   out of   435 routed (100.00%)
#5  Signal &quot;u8_ws2812.n31639&quot;
       Control loads: 0     out of    75 routed (  0.00%)
       Data    loads: 0     out of    24 routed (  0.00%)
---------------------------------------------------------
--------------------------------------------------------------------------------
Completed routing resource preassignment
WARNING &lt;70009502&gt; - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routing in Serial Mode ......
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Start NBR section for initial routing at 14:18:22 03/18/25
Level 4, iteration 1
758(0.29%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: 25.504ns/0.000ns; real time: 19 secs 

Info: Initial congestion level at 75.00% usage is 0
Info: Initial congestion area  at 75.00% usage is 0 (0.00%)

Start NBR section for normal routing at 14:18:39 03/18/25
Level 4, iteration 1
229(0.09%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: 24.381ns/0.000ns; real time: 21 secs 
Level 4, iteration 2
80(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: 23.852ns/0.000ns; real time: 22 secs 
Level 4, iteration 3
49(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: 23.693ns/0.000ns; real time: 23 secs 
Level 4, iteration 4
18(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: 23.693ns/0.000ns; real time: 23 secs 
Level 4, iteration 5
8(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: 23.693ns/0.000ns; real time: 23 secs 
Level 4, iteration 6
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: 23.693ns/0.000ns; real time: 23 secs 
Level 4, iteration 7
3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: 23.693ns/0.000ns; real time: 23 secs 
Level 4, iteration 8
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: 23.693ns/0.000ns; real time: 24 secs 
Level 4, iteration 9
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: 23.693ns/0.000ns; real time: 24 secs 
Level 4, iteration 10
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: 23.693ns/0.000ns; real time: 24 secs 

Start NBR section for setup/hold timing optimization with effort level 3 at 14:18:44 03/18/25

Start NBR section for post-routing at 14:18:46 03/18/25

End NBR router with 0 unrouted connection(s)
WARNING &lt;70009502&gt; - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

Checksum -- route: 5c24cfd1e2a974345373265ba626cb185e09aadd

Total CPU time 19 secs 
Total REAL time: 30 secs 
Completely routed.
End of route.  16777 routed (100.00%); 0 unrouted.

Writing design to file ICE40UP5K1_impl_1_par.dir/5_1.udb ...


All signals are completely routed.


PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Estimated worst slack&lt;setup/&lt;ns&gt;&gt; = 30.353
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Estimated worst slack&lt;hold/&lt;ns&gt;&gt; = 1.743
PAR_SUMMARY::Timing score&lt;hold/&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0

Note: user must run &apos;timing&apos; for timing closure signoff.

Total CPU  Time: 1 mins 17 secs 
Total REAL Time: 1 mins 29 secs 
Peak Memory Usage: 252.70 MB


par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2024 Lattice Semiconductor Corporation,  All rights reserved.



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</PRE></DIV>

<DIV id="toc" class="radiant"><span onmousemove="showTocList()">Contents</span>
<UL id="toc_list">
<LI><A href=#par_cts>Cost Table Summary</A></LI>
<LI><A href=#par_best>Best Par Run</A></LI>
<LI><A href=#par_constraint>Constraint Summary</A></LI>
<LI><A href=#par_dus>Device utilization summary</A></LI>
<LI><A href=#par_clk>Clock Report</A></LI>
</UL>
</DIV>

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